1. Field of the Invention
The present invention relates to a differential amplifier circuit used in an image input apparatus for, e.g., a video camera, digital still camera, and image scanner.
2. Related Background Art
In recent years, a cell size reduction of a photoelectric conversion element is strenuously being made using a micropatterning process to achieve higher resolution, and a photoelectric conversion signal output is lowering accordingly. Under the circumstance, an amplifier type solid-state image pickup device that can amplify and output a photoelectric conversion signal has received a lot of attention. As such amplifier type photoelectric conversion devices, MOS, AMI, CMD, BASIS devices, and the like are available. Of these devices, a MOS device accumulates photocarriers which is generated by a photodiode, in the gate electrode of a MOS transistor, and charge-amplifies and outputs its change in potential to an output unit in accordance with a drive timing from a scanning circuit. In recent years, of MOS devices, a CMOS solid-state image pickup device as well as its photoelectric conversion unit and peripheral circuit units, all of which are realized by CMOS processes has especially received a lot of attention.
FIG. 11 is a block diagram of a general CMOS solid-state image pickup device. In this example, the anodes of photodiodes D11 to D33 for generating photosignal charges are connected to the ground. The cathodes of the photodiodes D11 to D33 are connected to the gates of amplifier MOS transistors M311 to M333 via transfer MOS transistors M111 to M133. The gates of the amplifier MOS transistors M311 to M333 are connected to the sources of reset MOS transistors M211 to M233 used to reset the transistors M311 to M333. The drains of the reset MOS transistors M211 to M233 are connected to a reset power supply. Furthermore, the drains of the amplifier MOS transistors M311 to M333 are connected to a power supply, and their sources are connected to the drains of select MOS transistors M411 to M433.
The gate of the transfer MOS transistor M111 is connected to a first row select line (vertical scanning line) PTX1 that runs horizontally. The gates of similar transfer MOS transistors M121 and M131 of other pixels connected to the same row are also connected in common to the first row select line PTX1. The gate of the reset MOS transistor M211 is connected to a second row select line (vertical scanning line) PRES1 which runs horizontally. The gates of similar reset MOS transistors M211 and M231 of other pixels connected to the same row are also connected in common to the second row select line PRES1. The gate of the select MOS transistor M411 is connected to a third row select line (vertical scanning line) PSEL1 that runs horizontally. The gates of similar select MOS transistors M421 and M431 of other pixels connected to the same row are also connected in common to the third row select line PSEL1. These first to third row select lines are connected to a vertical scanning circuit 2, and receive signal voltages on the basis of operation timings to be described later. Pixels and row select lines with similar arrangements are connected to the remaining rows shown in FIG. 11. These row select lines receive signals PTX2 and PTX3, PRES2 and PRES3, and PSEL2 and PSEL3 generated by the vertical scanning circuit 2.
The source of the select MOS transistor M411 is connected to a vertical signal line V1 which runs vertically. The sources of similar MOS transistors M412 and M413 of pixels connected to the same column are also connected to the vertical signal line V1. The vertical signal line V1 is connected to a load MOS transistor N82 serving as a load means. The select MOS transistors and load MOS transistors are similarly connected to remaining vertical signal lines V2 and V3 shown in FIG. 11. Furthermore, the sources of the load MOS transistors N82 to N84 are connected to a common GND line 4, and their gates are connected to the gate of an input MOS transistor N81 and in common to a voltage input terminal 5.
Furthermore, the vertical signal line V1 is connected to a capacitor CTN1 used to temporarily hold a noise signal via a noise signal transfer switch N91, and also to a capacitor CTS1 used to temporarily hold a photosignal via a photosignal transfer switch N92. The terminals, opposite to the vertical signal line V1, of the noise signal holding capacitor CTN1 and photosignal holding capacitor CTS1 are connected to the ground. The node between the noise signal transfer switch N91 and noise signal holding capacitor CTN1, and the node between the photosignal transfer switch N92 and photosignal holding capacitor CTS1 are connected to the ground respectively via holding capacitor reset switches N92 and N98, and are connected to a differential amplifier circuit 7 used to calculate the difference between a photosignal and noise signal via horizontal transfer switches N913 and N914. The gates of the horizontal transfer switches N913 and N914 are connected in common to a column select line H1, and to a horizontal scanning circuit 3. Read circuits with similar arrangements are connected to remaining columns V2 and V3 shown in FIG. 11. The gates of the noise signal transfer switches N91, N93, and N95, and photosignal transfer switches N92, N94, and N96 are respectively connected in common to PTN and PTS, and receive signal voltages on the basis of operation timings to be described below.
The operation of the CMOS solid-state image pickup device shown in FIG. 11 will be described below with reference to FIG. 12. Prior to read processes of photosignal charges from the photodiodes D11 to D33, the gates PRES1 of the reset MOS transistors M211 to M231 change to high level. As a result, the gates of the amplifier MOS transistors M311 to M331 are reset to the reset power supply. After the gates PRES1 of the reset MOS transistors M211 to M231 return to low level, the gates PSEL1 of the select MOS transistors M411 to M431 and the gates PTN of the noise signal transfer switches N91, N93, and N95 change to high level. As a result, reset signals (noise signals) superposed with reset noise are read out to the noise signal holding capacitors CTN1 to CTN3.
Then, the gates PTN of the noise signal transfer switches N91, N93, and N95 return to low level. The gates PTX1 of the transfer MOS transistors M111 to M131 change to high level, and photosignal charges in the photodiodes D11 to D31 are transferred to the gates of the amplifier MOS transistors M311 to M331. After the gates PTX1 of the transfer MOS transistors M111 to M131 return to low level, the gates PTS of the photosignal transfer switches N92, N94, and N96 change to high level. As a result, photosignals are read out to the photosignal holding capacitors CTS1 to CTS3. The gates PTS of the photosignal transfer switches N92, N94, and N96 then return to low level. With the operations described so far, noise signals and photosignals of pixels connected to the first row are respectively held in the noise signal holding capacitors CTN1 to CTN3 and photosignal holding capacitors CTS1 to CTS3 connected to the respective columns.
The gates PRES1 of the reset MOS transistors M211 to M231 and the gates PTX1 of the transfer MOS transistors M111 to M131 change to high level to reset photosignal charges in the photodiodes D11 to D31. After that, the gates of the horizontal transfer switches N913 to N918 of respective columns change to high level in turn in response to signals H1 to H3 from the horizontal scanning circuit 3, and voltages held in the noise holding capacitors CTN1 to CTN3 and photosignal holding capacitors CTS1 to CTS3 are sequentially read out to the differential amplifier circuit 7. In between signal read processes of respective columns, the negative (inverting) and positive-phase (non-inverting) input terminals of the differential amplifier circuit 7 are reset to a reset voltage Vres of a horizontal output line by reset switches N919 and N920. The differential amplifier circuit 7 calculates the differences between photosignals and noise signals and sequentially outputs them onto an output terminal OUT. In this manner, the read processes of the pixels connected to the first row are completed.
After that, prior to read processes of the second row, the gates PCTR of reset switches N97 to N912 for the noise signal holding capacitors CTN1 to CTN3 and photosignal holding capacitors CTS1 to CTS3 change to high level to be reset to GND. Likewise, signals of pixels connected to the second and subsequent rows are sequentially read out in response to signals from the vertical scanning circuit 2, thus completing the read processes from all pixels.
In the aforementioned CMOS solid-state image pickup device, it is a common practice to use a differential amplifier circuit using an operational amplifier shown in FIG. 13 as the differential amplifier circuit used to calculate the difference between the photosignal and noise signal. The input/output characteristics in such differential amplifier circuit are determined by:                     Vout        =                                            Vinp              ·                              R94                ⁡                                  (                                      R91                    +                    R92                                    )                                                      -                          Vinn              ·                              (                                  R93                  +                  R94                                )                                                          R91            ·                          (                              R93                +                R94                            )                                                          (        1        )            If R91=R93 and R92=R94, we have:   Vout  =            (              Vinp        -        Vinn            )        ·          R92      R91      
However, when the aforementioned differential amplifier circuit is formed on a single semiconductor substrate such as a monocrystalline silicon substrate by the manufacturing technique of semiconductor integrated circuits, conditions R91=R93 and R92=R94 may deviate due to variations or the like in the manufacture.
For example, if R91=R93 and a R92=R94, equation (1) is rewritten as:   Vout  =                    (                  Vinp          -          Vinn                )            ·              R92        R91              +          Vinp      ·                                    (                          a              -              1                        )                    ⁢          R91                          R91          +                      a            ·            R92                              
This means that an output appears as Vout even when a signal Vinp=Vinn is input, and the common-mode rejection ratio (to be abbreviated as CMRR hereinafter) impairs. Consequently, the noise rejection ratio of the CMOS solid-state image pickup device impairs.